library IEEE;
use ieee.std_logic_1164.all;
use work.package_multi.all;

entity multi is
	generic(GND			: std_logic_vector (7 downto 0) := "00000000"
		   );
	port(data_in, adda_in, datb_in, addb_in    : in	std_logic_vector (7 downto 0);
		 reqa, reqb, rela, relb      		   : in   std_logic;
		 dat_out, add_out 	 		   : out	std_logic_vector (7 downto 0);
		 acka, ackb		        	 		   : out std_logic
		 );
end multi;

architecture arch_multi of multi is
	signal sel : std_logic;
	signal cs  : std_logic;


begin
	data_mux:mux port map (data_in, adda_in, datb_in, addb_in, sel, cs, dat_out, add_out);
	ref:referee port map (reqa, reqb, rela, relb, acka, ackb, sel, cs);
	
end arch_multi;